Demonstrates how to use the TX SWI library to control switching on a TX board. txsdemo tests communications between two TX boards that are connected with the H.100/H.110 bus or with T1/E1/J1 cables.
txsdemo [options]
where options are:
Option |
Description |
-m |
Sets the TX board number of the board that starts as clock master. Default: CP 1. |
-s |
Sets the TX board number of the board that starts as clock slave. Default: CP 2. |
-p |
Sets the number of test passes. Default: Infinite. |
-c |
Sets the host-side channel number. Default: 3. |
-t |
Performs a T1 test between the two TX boards. Default: Test H.100/H.110 connectivity. |
-e |
Performs an E1 test between the two TX boards. Default: Test H.100/H.110 connectivity. |
-j |
Performs a J1 test between the two TX boards. Default: Test H.100/H.110 connectivity. |
txsdemo tests connectivity between two TX boards identified as the initial master and slave boards. The master board begins the test as the board mastering the clock (H.100/H.110 A_CLOCK, or loop master for T1/E1/J1 test). After a test pass completes with the initial master/slave clocking, the master becomes the clock slave for the next pass.
The following table lists the stages of the connectivity test:
Stage |
Description |
1 |
CAPS. Retrieving the switching capabilities of the TX boards. |
2 |
CLOCK. Configuring clocking on the TX boards. |
3 |
CONFIG. Configuring T1/E1/J1 trunks. This step is skipped if testing over the H.100/H.110 bus. |
4 |
CONNECT. Making connections on the receiver board. |
5 |
PATTERN. Configuring output patterns on the transmitter board. |
6 |
SAMPLE. Collecting samples on the receiver board. |
7 |
BREAK. Breaking all connections defined for the given test pass. |
8 |
ADVANCE. Testing advance stream or trunk. If testing T1/E1/J1 connections, go to CLOCK phase. If testing H.100/H.110 connections, go to CONNECT phase. |
For the H.100/H.110 bus, the test begins with the master board transmitting patterns to the odd stream numbers. The slave board connects odd stream inputs to even stream outputs. After all connections are verified, the master board is changed to transmit patterns to the even stream numbers (with the slave board connecting even stream inputs to odd stream outputs).
Although txsdemo tests TX board connectivity, its main purpose is to demonstrate the use of the TX SWI library. Use the example source code as a starting point for other TDM switching control applications.
When txsdemo executes, a progress bar displays the current test phase:
----- H.100/H.110 Streams ------ | T1/E1/J1
1 2 3 | Framers
01234567890123456789012345678901 | 12345678
================================ | ========
################################ | ########
where # is the testing phase for the given H.100/H.110 stream or T1/E1/J1 trunk and is one of the following values:
Value |
Description |
_ |
Stream or trunk has not been tested. |
+ |
Making connections across a stream or trunk. |
* |
Sampling for expected patterns across a stream or trunk. |
x |
Breaking connections across a stream or trunk. |
. |
Pattern test PASSED for a stream or trunk. |
F |
Pattern test FAILED for a stream or trunk. |
txsdemo also supports the following single-character user commands, which can be entered from the keyboard:
Command |
Description |
k |
Displays the progress bar key. |
s |
Shows all pattern checking statistics. |
r |
Resets all pattern checking statistics (zeros all statistics). |
? |
Shows the set of supported keyboard commands. |
q |
Quits txsdemo. |